Memories typically include an array of memory cells arranged in rows and columns. Memory cells of each row are accessed by activating a corresponding access line often referred to as a word line. The word line may be activated by a word line driver responsive to decoding a corresponding row address with a row address decoder.
Word line drivers typically comprise a p-channel field effect transistor (pFET) and an n-channel field effect transistor (nFET) coupled together at their respective drains and gates, forming a complementary FET output stage coupled to the word line at the drains of the transistors. The source of the pFET can be configured to receive, for example, a phase signal (e.g., from a phase decoder). Meanwhile, the source of the nFET can be configured to receive, for example, a deactivated word line voltage (e.g., VNEGWL). Assuming a sufficiently high voltage phase signal (e.g., VCCP, which may be a pumped supply voltage) is provided as the phase signal to the source of its word line driver, a word line may be activated by providing a sufficiently low voltage (e.g., ground) to the gate of the pFET to turn on the pFET and pull the word line up to ˜VCCP. To deactivate the word line to close the row), as is typically desired after a row of memory cells has been accessed (e.g., refreshed, read or written), a sufficiently high voltage (e.g., VCCP) is provided to the gate of the nFET to quickly turn on the nFET and pull the word line down to ˜VNEGWL.
One of performance issues associated with the use of such a word line driver is a prolonged read-to-precharge time (tRP) from hot carrier degradation of nFET(s) in the word line driver due to aging stress. For each discharge of a word line, the source of the pFET may receive the phase signal PH in the inactive state and the GRF signal in the active state and the pFET and the nFET are configured to cause a signal level of the word line WL to transition to a logic low level. However, the signal level of the word line WL may not effectively transition to the logic low level responsive to the PH signal in the inactive state and the GRF signal in the inactive state within the tRP as designed, when the nFET has a higher drain-source voltage Vds, due to hot carrier degradation that keeps the signal level of the word line WL higher than the logic low level. In order to improve the word line driver's reliability by keeping the tRP short enough, maintaining a lower drain-source voltage Vds of the nFET and keeping a lower signal level (e.g., a negative voltage) of the word line WL may be desired when the signal level of the word line WL is supposed to transition from the logic high level to the logic low level (e.g., a falling edge of the word line WL).